Network Working Group Andrew G. Malis
Internet Draft Ken Hsu
Expiration Date: August 2001 Vivace Networks, Inc.
Steve Vogelsang
John Shirron
Laurel Networks, Inc.
Luca Martini
Level 3 Communications, LLC.
February 2001
SONET/SDH Circuit Emulation Service Over MPLS (CEM) Encapsulation
draft-malis-sonet-ces-mpls-02.txt
Status of this Memo
This document is an Internet-Draft and is in full conformance with
all provisions of Section 10 of RFC 2026 [1].
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1. Abstract
This document describes a method for encapsulating SONET/SDH Path
signals for transport across an MPLS network.
2. Conventions used in this document
The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT",
"SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in
this document are to be interpreted as described in RFC 2119 [2].
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3. Introduction
This document describes a method for encapsulating time division
multiplexed (TDM) digital signals (TDM circuit emulation) for
transmission over a packet-oriented MPLS network. The transmission
system for circuit-oriented TDM signals is the Synchronous Optical
Network (SONET)[3]/Synchronous Digital Hierarchy (SDH) [4]. To
support TDM traffic, which includes voice, data, and private leased
line service, the MPLS network must emulate the circuit
characteristics of SONET/SDH payloads. MPLS labels and a new
circuit emulation header are used to encapsulate TDM signals and
provide the Circuit Emulation Service over MPLS (CEM).
This document is closely related to references [5], which describes
the control protocol methods used to signal the usage of CEM, and
[6], which describes a related method of encapsulating Layer 2
frames over MPLS and which shares the same signaling.
4. Scope
This document describes how to provide CEM for the following digital
signals:
1. SONET STS-1 synchronous payload envelope (SPE)/SDH VC-3
2. STS-Nc SPE (N = 3, 12, or 48)/SDH VC-4, VC-4-4c, VC-4-16c
Other SONET/SDH signals, such as virtual tributary (VT) structured
sub-rate mapping, are not explicitly discussed in this document;
however, it can be extended in the future to support VT and lower
speed non-SONET services. OC-192c SPE/VC-4-64c are also not included
at this point, since most MPLS networks use OC-192c or slower
trunks, and thus would not have sufficient capacity. As trunk
capacities increase in the future, the scope of this document can be
accordingly extended.
5. CEM Encapsulation Format
A TDM data stream is segmented into packets and encapsulated in MPLS
packets. Each packet has one or more MPLS labels, followed by a 32-
bit CEM header to associate the packet with the TDM stream.
The outside label is used to identify the MPLS LSP used to tunnel
the TDM packets through the MPLS network (the tunnel LSP). The
interior label is used to multiplex multiple TDM connections within
the same tunnel. This is similar to the label stack usage defined
in [5] and [6].
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The 32-bit CEM header has the following format:
0 1 2 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
| Rsvd | Sequence Num | Structure Pointer |N|P| ECC-6 |
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
Figure 1. CEM Header Format
The above fields are defined as follows:
Reserved: These bits are reserved for future use.
Sequence Number: This is a packet sequence number, which
continuously cycles from 0 to 1023. It begins at 0 when a TDM LSP
is created.
Structure Pointer: The pointer points to the J1 byte in the payload
area. The value is from 0 to 1,022, where 0 means the first byte
after the CEM header. The pointer is set to 0x3FF (1,023) if a
packet does not carry the J1 byte. See [3] and [4] for more
information on the J1 byte and the structure pointer.
The N and P bits: See sections 6 and 7 for their definition.
ECC-6: An Error Correction Code to protect the CEM header. This
offers the ability to correct single bit errors and detect up to two
bit errors. The ECC algorithm is described in Appendix B.
6. Clocking Mode
It is necessary to be able to regenerate the input service clock at
the output interface. Two clocking modes are supported: synchronous
and asynchronous.
6.1 Synchronous
When synchronous SONET timing is available at both ends of the
circuit, the N(JE) and P(JE) bits are set for negative or positive
justification events. The event is carried in five consecutive
packets at the transmitter. The receiver plays out the event when
three out of five packets with NJE/PJE bit set are received. If both
bits are set, then path AIS event has occurred (this is further
discussed in section 7). If there is a frequency offset between the
frame rate of the transport overhead and that of the STS SPE, then
the alignment of the SPE shall periodically slip back or advance in
time through positive or negative stuffing. The N(JE) and P(JE) bits
are used to replay the stuff indicators and eliminate transport
jitter.
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6.2 Asynchronous
If synchronous timing is not available, the N and P bits are not
used for frequency justification and adaptive methods are used to
recover the timing. The N and P bits are only used for the
occurrence of a path AIS event. An example adaptive method can be
found in Section 3.4.2 of [7].
7. Circuit Outages
In a SONET/SDH network, circuit outages are signaled using
maintenance alarms such as Path AIS (AIS-P). In particular, AIS-P
indicates that the SONET Path is not currently transmitting valid
end-user data, and the SPE contains all one bits. To conserve
network bandwidth, the CEM header is used to indicate that the
emulated SONET Path is signaling AIS-P, and the actual one bits are
not transmitted.
In the CEM header, both the N and P bits are set to signal AIS-P.
When a CEM header is received with both bits set, the CEM receiver
transmits the AIS-P alarm out the associated TDM interface.
Note that the return RDI-P indication is contained, as usual, in the
G1 octet in the SONET header.
Also note that this differs from the outage mechanism in [5], which
withdraws labels as a result of an endpoint outage. TDM circuit
emulation requires the ability to distinguish between the de-
provisioning of a circuit, which would cause the labels to be
withdrawn, and temporary outages, which are signaled using AIS-P.
8. CEM LSP Signaling
For maximum network scaling, CEM LSP signaling may be performed
using the LDP Extended Discovery mechanism as augmented by the VC
FEC Element defined in [5]. MPLS traffic tunnels may be dedicated
to CEM, or shared with other MPLS-based services. The value 8008 is
used for the VC Type in the VC FEC Element in order to signify that
the LSP being signaled is to carry CEM. Note that the generic
control word defined in [6] is not used, as its functionality is
included in the CEM encapsulation header.
Alternatively, static label assignment may be used, or a dedicated
traffic engineered LSP may be used for each CEM circuit.
9. Open Issues
Future revisions of this draft will discuss underlying MPLS QoS
requirements and mechanisms for CEM, support for VT and lower speed
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non-SONET services, and sending additional maintenance alarms in
addition to AIS-P.
10. Security Considerations
As with [5], this document does not affect the underlying security
issues of MPLS.
11. Intellectual Property Disclaimer
This document is being submitted for use in IETF standards
discussions. Vivace Networks, Inc. has filed one or more patent
applications relating to the CEM technology outlined in this
document. Vivace Networks, Inc. will grant free unlimited licenses
for use of this technology.
12. References
[1] Bradner, S., "The Internet Standards Process -- Revision 3",
BCP 9, RFC 2026, October 1996.
[2] Bradner, S., "Key words for use in RFCs to Indicate Requirement
Levels", BCP 14, RFC 2119, March 1997
[3] American National Standards Institute, "Synchronous Optical
Network (SONET) - Basic Description including Multiplex
Structure, Rates and Formats," ANSI T1.105-1995.
[4] ITU Recommendation G.707, "Network Node Interface For The
Synchronous Digital Hierarchy", 1996.
[5] Martini et al, "Transport of Layer 2 Frames Over MPLS", draft-
martini-l2circuit-trans-mpls-05.txt, work in progress, February
2001.
[6] Martini et al, "Encapsulation Methods for Transport of Layer 2
Frames Over MPLS", draft-martini-l2circuit-encap-mpls-01.txt,
work in progress, February 2001.
[7] ATM Forum, "Circuit Emulation Service Interoperability
Specification Version 2.0", af-vtoa-0078.000, January 1997.
13. Acknowledgments
The authors would like to thank Mitri Halabi and Bob Colvin, both of
Vivace Networks, and Jeremy Brayley of Laurel Networks, for their
comments and suggestions.
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14. Authors' Addresses
Andrew G. Malis
Vivace Networks, Inc.
2730 Orchard Parkway
San Jose, CA 95134
Email: Andy.Malis@vivacenetworks.com
Ken Hsu
Vivace Networks, Inc.
2730 Orchard Parkway
San Jose, CA 95134
Email: Ken.Hsu@vivacenetworks.com
Steve Vogelsang
Laurel Networks, Inc.
2706 Nicholson Rd.
Sewickley, PA 15143
Email: sjv@laurelnetworks.com
John Shirron
Laurel Networks, Inc.
2607 Nicholson Rd.
Sewickley, PA 15143
Email: jshirron@laurelnetworks.com
Luca Martini
Level 3 Communications, LLC.
1025 Eldorado Blvd.
Broomfield, CO 80021
Email: luca@level3.net
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Appendix A. SONET/SDH Rates and Formats
For simplicity, the discussion in this section uses SONET
terminology, but it applies equally to SDH as well. SDH-equivalent
terminology is shown in the tables.
The basic SONET modular signal is the synchronous transport signal-
level 1 (STS-1). A number of STS-1s may be multiplexed into higher-
level signals denoted as STS-N, with N synchronous payload envelopes
(SPEs). The optical counterpart of the STS-N is the Optical Carrier-
level N, or OC-N. Table 1 lists standard SONET line rates discussed
in this document.
OC Level OC-1 OC-3 OC-12 OC-48 OC-192
SDH Term - STM-1 STM-4 STM-16 STM-64
Line Rate(Mb/s) 51.840 155.520 622.080 2,488.320 9,953.280
Table 1. Standard SONET Line Rates
Each SONET frame is 125 ´s and consists of nine rows. An STS-N frame
has nine rows and N*90 columns. Of the N*90 columns, the first N*3
columns are transport overhead and the other N*87 columns are SPEs.
A number of STS-1s may also be linked together to form a super-rate
signal with only one SPE. The optical super-rate signal is denoted
as OC-Nc, which has a higher payload capacity than OC-N.
The first 9-byte column of each SPE is the path overhead (POH) and
the remaining columns form the payload capacity with fixed stuff
(STS-Nc only). The fixed stuff, which is purely overhead, is N/3-1
columns for STS-Nc. Thus, STS-1 and STS-3c do not have any fixed
stuff, STS-12c has three columns of fixed stuff, and so on.
The POH of an STS-1 or STS-Nc is always nine bytes in nine rows. The
payload capacity of an STS-1 is 86 columns (774 bytes) per frame.
The payload capacity of an STS-Nc is (N*87)-(N/3) columns per frame.
Thus, the payload capacity of an STS-3c is (3*87 - 1)*9 = 2,340
bytes per frame. As another example, the payload capacity of an STS-
192c is 149,760 bytes, which is exactly 64 times larger than the
STS-3c.
There are 8,000 SONET frames per second. Therefore, the SPE size,
(POH plus payload capacity) of an STS-1 is 783*8*8,000 = 50.112
Mb/s. The SPE size of a concatenated STS-3c is 2,349 bytes per frame
or 150.336 Mb/s. The payload capacity of an STS-192c is 149,760
bytes per frame, which is equivalent to 9,584.640 Mb/s. Table 2
lists the SPE and payload rates supported.
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SONET STS Level STS-1 STS-3c STS-12c STS-48c STS-192c
SDH VC Level - VC-4 VC-4-4c VC-4-16c VC-4-64c
Payload Size(Bytes) 774 2,340 9,360 37,440 149,760
Payload Rate(Mb/s) 49.536 149.760 599.040 2,396.160 9,584.640
SPE Size(Bytes) 783 2,349 9,396 37,584 150,336
SPE Rate(Mb/s) 50.112 150.336 601.344 2,405.376 9,621.504
Table 2. Payload Size and Rate
To support circuit emulation, the entire SPE of a SONET STS or SDH
VC level is encapsulated into packets, using the encapsulation
defined in section 5, for carriage across MPLS networks.
Appendix B. ECC-6 Definition
ECC-6 is an Error Correction Code to protect the CEM header. This
provides single bit correction and the ability to detect up to two
bit errors.
Error Correction Code:
|---------------Header bits 0-25 -------------------| ECC-6 code|
0 1 2 3
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
|1 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 1|1 0 0 0 0 0|
|1 1 1 1 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 1 1 1 1 1 1 1|0 1 0 0 0 0|
|1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1|0 0 1 0 0 0|
|0 1 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 1|0 0 0 1 0 0|
|0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0|0 0 0 0 1 0|
|0 0 0 1 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 1 1|0 0 0 0 0 1|
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
Figure 2. ECC-6 Check Matrix X
The ECC-6 code protects the 32 bit CEM header as follows:
The encoder generates the 6 bit ECC using the matrix shown in Figure
2. In brief, the encoder builds another 26 column by 6 row matrix
and calculates even parity over the rows. The matrix columns
represent CEM header bits 0 through 25.
Denote each column of the ECC-6 check matrix by X[], and each column
of the intermediate encoder matrix as Y[]. CEM[] denotes the CEM
header and ECC[] is the error correction code that is inserted into
CEM header bits 26 through 31.
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for i = 0 to 25 {
if CEM[i] = 0 {
Y[i] = 0;
} else {
Y[i] = X[i];
}
}
In other words, for each CEM header bit (i) set to 1, set the
resulting matrix column Y[i] according to Figure 2.
The final ECC-6 code is calculated as even parity of each row in Y
(i.e. ECC[k]=CEM[25+k]=even parity of row k).
The receiver also uses matrix X to calculate an intermediate matrix
YÆ based on all 32 bits of the CEM header. Therefore YÆ is 32
columns wide and includes the ECC-6 code.
for i = 0 to 31 {
if CEM[i] = 0 {
YÆ[i] = 0;
} else {
YÆ[i] = X[i];
}
}
The receiver then appends the incoming ECC-6 code to Y as column 32
(ECC[0] should align with row 0) and calculates even parity for each
row. The result is a single 6 bit column Z. If all 6 bits are 0,
there are no bit errors (or at least no detectable errors).
Otherwise, it uses Z to perform a reverse lookup on X[] from Figure
2. If Z matches column X[i], then there is a single bit error. The
receiver should invert bit CEM[i] to correct the header. If Z fails
to match any column of X, then the CEM header contains more than one
bit error and the CEM packet MUST be discarded.
Note that the ECC-6 code provides single bit correction and 2-bit
detection of errors within the received ECC-6 code itself.
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